With the increasing integration density of semiconductor devices, individual semiconductor devices, especially, MOSFETs, have been scaled down. Also, as sub-micron MOSFETs are being more widely used, channel regions disposed between sources and drains are becoming shorter. These changes may cause short channel effects, such as a drop in the threshold voltage of the MOSFET and/or punch-through. To suppress these short channel effects, a method of forming pocket regions by implanting impurity ions between a source or drain region and a channel region under a gate electrode has been proposed.
FIG. 1 is a cross-sectional view of a MOSFET with conventional pocket regions that is disclosed in U.S. Pat. No. 5,733,792. Hereinafter, a conventional method of fabricating a MOSFET with pocket regions will be briefly described with reference to FIG. 1.
As seen in FIG. 1, field oxide layers 2 are selectively formed on the surface of a silicon substrate 1 using local oxidation of silicon (LOCOS), and impurity ions are implanted into the silicon substrate 1 to adjust the threshold voltage. Afterwards, a gate oxide layer 3 is formed on the surface of the silicon substrate 1 using thermal oxidation of silicon. Next, a polysilicon layer 4 is deposited on the gate oxide layer 3 and is then subject to photolithographic and etching processes, thereby completing a polysilicon gate electrode 4.
Next, a silicon oxide layer is deposited on the entire surface of the silicon substrate 1 and anisotropically etched such that silicon oxide spacers 5 are formed on the sidewalls of the polysilicon gate electrode 4. Then, impurity ions are implanted into the silicon substrate 1 using the gate electrode 4 and the spacers 5 as an ion implantation mask, thereby forming source/drain regions 7.
Next, silicon selective growth layers 8 are formed on the source/drain regions 7 through epitaxial growth so as to have a high etch selectivity with respect to the silicon oxide spacers 5. The silicon selective growth layers 8 have facets 9 that face the silicon oxide spacers 5. The facets 9 are almost linearly sloped down to the bottoms of the silicon oxide spacers 5.
Next, impurity ions 10 are obliquely implanted into the silicon substrate 1 using the silicon oxide spacers 5 and the silicon selective growth layers 8 as an ion implantation mask such that pocket regions 11 are formed to be in contact with inside edge portions of the source/drain regions 7.
In the above method, an implantation angle of the impurity ions for forming the pocket regions 11 may be directly affected by the inclination angle of the facets 9 of the silicon selective growth layer 8. Accordingly, to form the pocket regions 11 only at inside edge portions of the source/drain region 7, the height and the angle of the facets 9 of the silicon selective growth layers 8, typically, must be very finely controlled.
Also, in the above conventional method, the silicon oxide spacers 5, which are formed on the sidewalls of the gate electrode 4, are in contact with the silicon selective growth layers 8 having the facets 9 at the outside bottom edges. Thus, when the pocket regions 11 are formed by implanting the impurity ions 10, the concentration and the profile of the pocket regions 11 vary according to not only the materials constituting the silicon selective growth layer 8 and the silicon oxide spacers 5, which function as the ion implantation mask, but also the height of the ion implantation mask, which may be varied based on the implantation angle used to implant the impurity ions through the mask regions. Therefore, it may be difficult to precisely adjust the concentration and the profile of the pocket regions 11.